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Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026
medium.com·2d
🗂️mmap
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Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
semiwiki.com·1d
📏Picolibc
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OPTIMUM-DERAM: Highly Consistent, Scalable, and Secure Multi-Object Memory using RLNC
arxiv.org·15h
🚧Memory Barriers
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A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)
semiengineering.com·2h
🔄Hardware Transactional Memory
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FlashAttention 4: Faster, Memory-Efficient Attention for LLMs
digitalocean.com·8h
🔄Hardware Transactional Memory
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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
danglingpointers.substack.com·1d·
Discuss: Substack
🧵Lightweight Threads
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One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
riscv.org·55m
RISC-V
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Lock Management Inside a Process: Why Native Locks Alone Are Not Enough
dev.to·1h·
Discuss: DEV
🔒Futex
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ANN v3: 200ms p99 query latency over 100 billion vectors
turbopuffer.com·20h·
Discuss: Hacker News
🌊Memory Bandwidth
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Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms
dev.to·18h·
Discuss: DEV
🧩mimalloc
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AMD MI455X Could Combine HBM4 And LPDDR For Massive AI Memory Capacity
hothardware.com·1d
💾HBM
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Weird RAM issue
68kmla.org·13h
🔄Memory Disambiguation
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GPU-Resident Inverted File Index for Streaming Vector Databases
arxiv.org·15h
🚀Milvus
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Silicon $T$-center hyperfine structure and memory protection schemes
link.aps.org·16h
🔄Hardware Transactional Memory
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Introducing PCIem
cakehonolulu.github.io·1d
💾PMem Programming
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Memory layout matters: Reducing metric storage overhead by 4x in a Rust TSDB
baarse.substack.com·5h·
Discuss: r/rust
🏛️Region-Based Memory
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TigerBeetle vs PostgreSQL Performance: Benchmark Setup, Local Tests
softwaremill.com·1d
🐅TigerBeetle Protocol
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Power-Efficient Processor Leverages Novel Dataflow Architecture
electronicdesign.com·2d·
Discuss: r/embedded
Hardware Acceleration
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Micron accelerates DRAM expansion through cooperation with Powerchip
igorslab.de·1d
🌊Memory Bandwidth
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Gated DeltaNet: The “Surgical Eraser” Solving Linear Attention’s Memory Problem
pub.towardsai.net·15h
📱Edge AI
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