🧩 Memory Interleaving - hello · Scour

Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026

medium.com·2d

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

semiwiki.com·1d

OPTIMUM-DERAM: Highly Consistent, Scalable, and Secure Multi-Object Memory using RLNC

arxiv.org·15h

🚧Memory Barriers

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)

semiengineering.com·2h

🔄Hardware Transactional Memory

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·8h

🔄Hardware Transactional Memory

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·55m

Lock Management Inside a Process: Why Native Locks Alone Are Not Enough

dev.to·1h·

Discuss: DEV

ANN v3: 200ms p99 query latency over 100 billion vectors

turbopuffer.com·20h·

Discuss: Hacker News

🌊Memory Bandwidth

Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms

dev.to·18h·

Discuss: DEV

AMD MI455X Could Combine HBM4 And LPDDR For Massive AI Memory Capacity

hothardware.com·1d

Weird RAM issue

68kmla.org·13h

🔄Memory Disambiguation

GPU-Resident Inverted File Index for Streaming Vector Databases

arxiv.org·15h

Silicon $T$-center hyperfine structure and memory protection schemes

link.aps.org·16h

🔄Hardware Transactional Memory

Introducing PCIem

cakehonolulu.github.io·1d

💾PMem Programming

Memory layout matters: Reducing metric storage overhead by 4x in a Rust TSDB

baarse.substack.com·5h·

Discuss: r/rust

🏛️Region-Based Memory

TigerBeetle vs PostgreSQL Performance: Benchmark Setup, Local Tests

softwaremill.com·1d

🐅TigerBeetle Protocol

Power-Efficient Processor Leverages Novel Dataflow Architecture

electronicdesign.com·2d·

Discuss: r/embedded

⚡Hardware Acceleration

Micron accelerates DRAM expansion through cooperation with Powerchip

igorslab.de·1d

🌊Memory Bandwidth

Gated DeltaNet: The “Surgical Eraser” Solving Linear Attention’s Memory Problem

pub.towardsai.net·15h

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